Vertical III-V Nanowires For In-Memory Computing

In recent times, deep neural networks (DNNs) have demonstrated great potential in various machine learning applications,such as image classification and object detection for autonomous driving. However, increasing the accuracy of DNNsrequires scaled, faster, and more energy-efficient hardware, which is limited by the von Neumann architecture whereseparate memory and computing units lead to a bottleneck in performance. A promising solution to address the vonNeumann bottleneck is in-memory computing, which can be achieved by integrating non-volatile memory cells such asRRAMs into dense crossbar arrays. On the hardware side, the 1-transistor-1-resistor (1T1R) configuration has been centralto numerous demonstrations of reservoir, in-memory and neuromorphic computing.In this thesis, to achieve a 1T1R cell with a minimal footprint of 4F2, a technology platform has been developed to integrate avertical nanowire GAA MOSFET as a selector device for the RRAM. Firstly, the effect of the geometry (planar to vertical) ofthe ITO/HfO2/TiN RRAM cell was studied where low energy switching (0.49 pJ) and high endurance (106) were achievedin the vertical configuration. Furthermore, InAs was incorporated as the GAA MOSFET selector channel material toleverage the beneficial transport properties of III-V materials desirable for supply voltage scaling. Finally, an approach wasdeveloped wherein InAs is used as the selector channel as well as the RRAM electrode by carefully tuning the InAs nativeoxides. This thesis also presents low-frequency noise characterization of the RRAM cell as well as the MOSFET to furtherunderstand the semiconductor/oxide interface. The vertical 1T1R cell developed in this thesis enables the implementationof Boolean logic operations using a single vertical nanowire while reducing the footprint by 51x when compared to itstraditional CMOS counterpart

Low-Frequency Noise in Vertical InAs/InGaAs Gate-All-Around MOSFETs at 15 K for Cryogenic Applications

Low-frequency noise (LFN), or 1/ f -noise, can be used effectively to evaluate device reliability which is a major concern in analog as well as digital circuits. In this work, we present 1/ f -noise characterization of vertical InAs/InGaAs gate-all-around (GAA) MOSFETs with a 70-nm gate length ( LG ) measured at cryogenic temperatures down to 15 K. The measurements at cryogenic temperatures reveal that the physical mechanism of 1/ f -noise changes from carrier number fluctuations at 300 K to mobility fluctuations at 15 K. We conclude that the channel conduction at 15 K is dominated by the nanowire core instead of the nanowire surface due to the effect of the border and interface traps freezing out. Vertical InAs/InGaAs GAA MOSFETs at 15 K, due to reduced surface scattering, exhibit a low value of Hooge parameter, αH ~ 5×10-6 and also have a low input-referred gate voltage noise spectral density, SVG=4.3μV2μm2 Hz -1 that are important for reliable cryogenic circuit applications

The Effect of Deposition Conditions on Heterointerface-Driven Band Alignment and Resistive Switching Properties

Titanium nitride and hafnium oxide stack have been widely used in various resistive memory elements since the materials are complementary-metal-oxide-semiconductor compatible. The understanding of the interface properties between the electrode and the oxide is important in designing the memory behavior. To bridge this understanding, HfOx grown using plasma enhanced atomic layer deposition (PEALD) and thermal atomic layer deposition (TALD) are compared, in terms of band alignment and electrical performances in the HfOx/PEALD TiN stacks. X-ray photoelectron spectroscopy reveals a thicker interfacial TiO2 layer in the PEALD HfOx/TiN stack whose interface resembles more to the PEALD HfOx/TiO2 interface (conduction band offset ΔEC = 1.63 eV), whereas the TALD HfOx stack interface resembles more to the TALD HfOx/TiN interface (ΔEC = 2.22 eV). The increase in the forming voltage and the early onset of reverse filament formation (RFF) in the I–V measurements for the PEALD HfOx stack confirms the presence of the thicker interfacial layer; the early onset of RFF is likely related to a smaller ΔEC. The findings show the importance of understanding the intricate details of the material stack, where ΔEC difference and the presence of a thicker TiO2 interfacial layer due to different deposition procedures affect the device performance

Effects of Interface Oxidation on Noise Properties and Performance in III–V Vertical Nanowire Memristors

Memristors implemented as resistive random-access memories (RRAMs) owing to their low power consumption, scalability, and speed are promising candidates for in-memory computing and neuromorphic applications. Moreover, a vertical 3D implementation of RRAMs enables high-density crossbar arrays at a minimal footprint. Co-integrated III–V vertical gate-all-around MOSFET selectors in a one-transistor-one-resistor (1T1R) configuration have recently been demonstrated where an interlayer (IL)-oxide has been shown to enable high RRAM endurance needed for applications like machine learning. In this work, we evaluate the role of the IL-oxide directly on InAs vertical nanowires using low-frequency noise characterization. We show that the low-frequency noise or the 1/f-noise in InAs vertical RRAMs can be reduced by more than 3 orders of magnitude by engineering the InAs/high-k interface. We also report that the noise properties of the vertical 1T1R do not degrade significantly after RRAM integration making them attractive to be used in emerging electronic circuits

A 4F2 Vertical Gate-all-around Nanowire Compute-in-memory Device Integrated in (1T1R) Cross-Point Arrays on Silicon

Complete 4F2 vertical nanowire (VNW) 1T1R cells with 106 cycles switching endurance and with a demonstrated capability of performing Boolean logic are fabricated and characterized in cross-point arrays. The performance of the vertical 1T1R cell is benefited from using the same III-V/high- k interface both for the vertical GAA MOSFET selector as well as the ReRAM. In this paper, we also compare the InAs nanowire implementation to a nanowire with an InGaAs top segment to utilize the relatively larger bandgap of InGaAs to reduce sneak-path leakage currents

Controlling Filament Stability in Scaled Oxides (3 nm) for High Endurance (>106) Low Voltage ITO/HfO2 RRAMs for Future 3D Integration

Non-volatile resistive-random-access-memories (RRAMs), which are highly scalable, cost-efficient and fast, are needed to meet the future computational needs beyond the traditional von-Neumann architecture. Oxygen vacancy RRAMs in particular have been demonstrated to operate at nanosecond programming ranges with low voltages as well as being integrated in dense cross-point arrays [1] . ITO/HfO 2 based RRAMs have emerged as a promising material stack due to its ultra-low switching voltages, self-compliance properties and the transparency of ITO that extends the material stack’s applications into display/wearable electronics [2] . As the different RRAM technologies are reaching maturity, scaling down the oxide thicknesses is now becoming vital for compatibility with dense 3D integration as projected by the IRDS 2020 [3] . We report that, when operated at relevant current levels (sub 100 µA), the filament integrity of ITO/HfO2 RRAM with a thin high-k oxide (3 nm) can be controlled depending on the deposition conditions, where a thermal ALD (TALD) process results in a stable filament formation as compared to a plasma enhanced ALD (PEALD) process used for depositing HfO2 . Our results further indicate that the RRAM RESET is more gradual for the TALD (oxygen deficient) HfO2 as compared to the abrupt switching behavior for the PEALD (oxygen rich) HfO2

Ultra-Scaled AlOx Diffusion Barriers for Multibit HfOx RRAM Operation

For dense very large scale integration (VLSI) of high performance, multibit resistive memory (RRAM), scalability of material dimensions, as well as the operational sensitivity of the RRAM to voltage fluctuations, have to be considered. This report presents the benefits of adding 0.5-nm thick AlO x diffusion barriers at the different electrode interfaces of HfO x . It is found that implementing AlO x -layers at both the bottom and the top electrode interface enables a tight control of the oxygen vacancy filament, resulting in low switching voltages and significantly improving switching endurance up to 10 6 cycles using a performance limiting resistor compliance. It is also shown that the filament in its low resistive state ( RLRS ) can be linearly reduced and enlarged at levels compatible to the conduction limitations of scaled selectors using an external 1T1R transistor compliance. With selector controlled resistance modulation, the RLRS becomes independent of the magnitude of the programming voltage and thus less sensitive to losses throughout a large memory array

Investigation of Reverse Filament Formation in ITO/HfO2-based RRAM

To overcome the large discrepancy in speed between computational devices and that of contemporary large capacity non-volatile memory (NVM) technologies, resistive random access memory (RRAM) technologies are seen as promising candidates, offering speed/energy improvements in several orders of magnitude while being 3D integration compatible [1]. Indium-Tin-Oxide (ITO) has several unique properties for RRAM operation, perhaps most prominently the self-compliance and an ultra-low switching voltage (±200 mV) [2]. We report on considerations for ITO electrical bottom electrode (BE) RRAM where we vary the ALD oxide deposition parameters in order to improve the reverse filament formation (RFF) occurring at large reset voltages. RFF is when the conducting filament is reformed. One of the key parameters of RRAM is the endurance, how many times it can switch before failure. The RFF is one of the limitations in the number of switches until a device reaches failure and it is thus of high importance to ensure a sufficient margin between the highest applied reset voltage and the RFF voltage not to compromise the endurance. We optimized the oxide to improve the RFF properties

Self-Heating in Gate-All-Around Vertical III-V InAs/InGaAs MOSFETs

We investigate self-heating in vertical, gate-all-around III-V InAs/InGaAs nanowire MOSFETs using pulsed IV measurements at various temperatures. Low temperature measurements reveal a negative output conductance indicating self-heating in the transistor. Under pulsed measurements, an increase in drain current (15%) and transconductance (30%) are observed at room temperature, with values influenced by the pulse width. This effect on performance is quantified with determination of the thermal resistance and capacitance. Furthermore, a first order thermal circuit is modelled based on the thermal impedances. The results indicate that the intrinsic temperature rises to 385 K when the device is operated in DC at room temperature (300 K) with a thermal time constant of 1~μ s. We find that self-heating is a limiting factor for device performance

Optimization of Platinum dioxide properties by plasma oxidation of sputtered PtOx

We have previously used reactively sputtered Platinum oxide thin film as DNA sensing element. In this work, we subject the reactively sputtered Platinum oxide thin films to an additional RIE step for 3, 6 and 9 min and carry out a detailed comparative study of the material and electrical properties of these films. XRD and XPS analysis revealed that when the reactively sputtered Platinum oxide film was subjected to RIE step for longer periods of time, it became progressively α-PtO2 in nature. Activation energies of 0.24 eV, 0.26 eV, 0.29 eV and 0.31 eV were obtained for the as deposited film and the films subjected to RIE step for 3, 6 and 9 min respectively. The Hall mobility of the as deposited Platinum oxide film was found to be 32.15 cm2V−1s−1 at room temperature. However, when the as deposited film was subjected to RIE step for 9 min the mobility value rises to as high as 136.13 cm2V−1s−1 at room temperature